Field-Effect Transistors in Integrated Circuits

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They can be analog or digital. Transistors, used to amplify and switch signals, heralded the modern electronics era. Transistors consist of three pins called an emitter, a collector and a base. The base controls the electric current, the collector handles the flow of the base current, and the emitter is where the current flows out. They can both work as transducers for electrochemical sensors.

Bipolar Junction Transistor (BJT)

A BJT Bipolar Junction Transistor combines two junction diodes from either a p-type semiconductor between to n-type semiconductors or a layer of n-type semiconductor between two p-type semiconductors. The BJT is a current-controlled device with a base circuit, essentially a current amplifier. In BJTs, the current travels through the transistor across holes or bonding vacancies with positive polarity and electrons with negative polarity. BJTs are used in many applications including analog and high power circuits. They were the first mass-produced type of transistor.

It has a gate terminal rather than a base, separated from other terminals by oxide film. This oxide layer serves as an insulator. The VSS supply voltage is applied directly to one emitter of T2 and to the base of T2 through a resistor R2 representing the resistance through region 12 between region 16 and the base of T2. This circuit can be recognized as the well known equivalent circuit of a silicon controlled rectifier SCR having its anode 30 connected to the VDD supply, its cathode 31 connected to the VSS supply, and its anode gate 32 and cathode gate 33 both connected to a common terminal.

For example, if the output terminal of the CMOS circuit receives a transient pulse having a voltage sufficiently greater than VDD, T1 is driven into conduction causing current to flow through R2. If the current through R2 were sufficiently large, the voltage drop across R2 would drive T2 into conduction causing current to flow through R1. If the current through R1 were sufficiently large, the voltage drop across R1 would maintain T1 in its conduction state even after the transient pulse has passed. Thus, under appropriate conditions once the SCR circuit is triggered, each transistor acts to keep the other in its conduction state and the SCR circuit remains latched until the bias voltage across the circuit VDD-VSS is interrupted or reduced below a level required to sustain conduction.

The SCR circuit may also be triggered by a transient pulse having a voltage sufficiently lower than VSS which when applied to the output terminal would initiate latchup by driving T2 into conduction. This condition is easily met in most conventional CMOS structures.


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The present invention provides a solution to the latchup problem which is effective for circuits of any packing density. The solution is based on the elimination of the parasitic circuit of FIG. This is achieved by a structure in which preferabvly at least one of a pair of complementary field-effect transistors comprise source and drain connections which are incapable of injecting minority carriers into the underlying bulk region. As with the structure shown in FIG. The substrate has a n-type bulk region 11 which is electrically connected to the VDD supply terminal through a n-type contact region 40 and a p-type "tub" region 12 which is electrically connected to the VSS supply terminal through a p-type contact region The n-channel transistor Q2 as before comprises heavily doped n-type source and drain regions 42 and 43 formed in the p-type tub region 12, and a polycrystalline silicon gate 44 overlying a gate insulator region The source region 42 is electrically connected to the VSS supply terminal via a metallic path 46 and the drain region 43 is electrically connected to the output terminal.

The p-channel transistor Q2 comprises platinum silicide PtSi Schottky barrier source and drain connections formed by thin PtSi layers 47 and 48 which are in contact with the surface of the lightly doped n-type bulk region 11, and a polycrystalline silicon gate 49 overlying a gate oxide layer The PtSi layer is typically about Angstroms thick. The formation of a Schottky barrier connection with PtSi on n-type silicon is known.

A method for making such connections is described in U. The source connection 47 is electrically connected to the VDD supply terminal via a metallic path 51 and the drain connection 48 is electrically connected to the output terminal. An appropriately formed field SiO 2 layer 52 provides electrical insulation between the semiconductor surface and the metallic paths 46 and In the preferred embodiment the metallic contacts and paths are formed with aluminum.

Insulated-gate field-effect transistors which use Schottky barrier contacts for the source and drain sometimes referred to as SB-IGFETs are now well known. However, such devices have heretofore not been used in complementary field-effect transistor circuits nor has the advantageous use of such devices to provide a CMOS circuit configuration free of parasitic SCR structures been previously recognized.

The Schottky barrier source and drain connections of transistor Q1 are advantageously formed with PtSi-Si contacts which have a barrier height of 0.

The process used to fabricate the structure of FIG. The modifications include the omission of the steps for forming the p-type source and drain regions of the p-channel transistor and the addition of steps for forming a PtSi layer over those portions of the silicon surface in which the p-type source and drain regions would have been formed.

Aluminum contacts 53 and 54 are made directly to the PtSi layers. The parasitic elements associated with the preferred embodiment are shown schematically in FIG. Owing to the absence of the p-type source and drain regions of Q1, the parasitic pnp transistor normally associated with the p-channel device has been eliminated and is replaced by Schottky diodes SD1 and SD2 which do not inject minority carriers into the n-type bulk region Since the source and drain regions of the n-channel device Q2 have not been eliminated, the parasitic npn transistor T2 remains.

The circuit formed by the parasitic elements of the preferred embodiment is illustrated schematically in FIG. While a transient pulse having a voltage sufficiently lower than VSS when applied to the emitter 51 of T2 would cause conduction between the VDD and VSS terminals through T2, this conduction is not self-sustained after the transient pulse has passed. Therefore, the structure of FIG.

In some instances it may be preferrable to provide the n-channel transistor with appropriately formed Schottky barrier contact source and drain instead of the p-channel transistor.

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In either instance the parasitic SCR structure would be eliminated in accordance with the present invention. It will be appreciated that the circuit structure shown in FIG. For some applications it may not be necessary to provide latchup protection to all adjacent complementary pairs of transistors in the circuit where only those pairs which have their drains connected to the external terminals of the circuit chip are subject to transient noise pulses which can cause latchup.

Therefore, for such circuits it may be preferrable to provide only those pairs of complementary transistors having drains connected to external terminals with SB-IGFETs.

MOS field-effect transistors and integrated circuits

It will be understood by those skilled in the art that the foregoing and other modifications and changes may be made to the described embodiments without departing from the spirit and scope of the invention. For example, numerous metal-semiconductor systems may be used to form appropriate Schottky barrier connections for the transistors; the complementary IGFET circuit may be formed by providing an n-type tub region in a p-type bulk region, the bulk region in which the circuit is formed may be an epitaxial layer; other materials may be substituted for the substrate, the gate insulator layer, the field insulator layer, and the gate electrode; and numerous techniques are available for forming the various regions of the device.

Although the preferred embodiment utilizes SB-IGFETs to avoid the latchup problem, the use of other types of field-effect transistors having non-injecting source and drain is also within the contenplation of the present invention. In the preferred embodiment, the n-channel device of an adjacent complementary pair of transistors in a CMOS circuit is provided with diffused source and drain while the p-channel device of the pair is provided with PtSi-Si Schottky barrier contact source and drain.

Such a structure completely eliminates the parasitic pnpn structure which causes the latchup problem in conventional CMOS structures. I claim: 1. A complementary field-effect transistor integrated circuit device comprising a semiconductive body having a first bulk region of one conductivity type extending from a surface of the body; a second bulk region, of a conductivity type which is opposite to the one type, extending from the surface; and a pair of complementary transistors adjacent the surface, one of the pair being of the opposite channel conductivity type and having spaced source and drain situated in the first bulk region, the other of the pair being of the one channel conductivity type and having spaced source and drain situated in the second bulk region; characterized in that the source and drain of at least one of the complementary pair of transistors each consists of a connection that is substantially incapable of injecting minority carriers when forward biased with respect to the bulk region in which the connection is situated whereby there are avoided the parasitic conditions for latchup.

An integrated circuit device of claim 1 further characterized in that the connection that is substantially incapable of injecting minority carriers is a Schottky barrier connection. An integrated circuit device of claim 1 wherein the one conductivity type is n-type and the opposite conductivity type is p-type and further characterized in that the source and drain of the n-channel conductivity type transistor each comprise a relatively heavily doped n-type region formed in the second bulk region and further characterized in that the source and drain of the p-channel conductivity type transistor each consists of a Schottky barrier connection made to the surface of the first bulk region.

The integrated circuit device of claim 3 wherein the semiconductive body is silicon and further characterized in that Schottky barrier connections of the source and drain of the p-channel conductivity type transistor each comprise a PtSi layer in contact with the surface of the first bulk region. DE DED1 en USA en. EPB1 en.

Insulated-gate Field-effect Transistors (MOSFET) | Solid-state Device Theory | Electronics Textbook

JPSB2 en. CAA en. GBB en. WOA1 en. Integrated electron circuits having Schottky field effect transistors of P- and N-type. Semiconductor device having a protection breakdown diode on a semi-insulative substrate. Integrated circuit in complementary circuit technology comprising a substrate bias voltage generator and a Schottky diode. Semiconductor device reducing internal noises and integrated circuit employing the same. Semiconductor systems utilizing materials that form rectifying junctions in both N and P-type doping regions, whether metallurgically or field induced, and methods of use.

USB1 en.


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Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts. Transistor having high dielectric constant gate insulating layer and source and drain forming schottky contact with substrate.